Frequency Divider as a Continuum

Frequency locking in an injection-locked frequency divider equation

We consider a model for a resonant injection-locked frequency divider, and study analytically the locking onto rational multiples of the driving frequency. We provide explicit formulae for the width of the plateaux appearing in the devil’s staircase structure of the lockings, and in particular show that the largest plateaux correspond to even integer values for the ratio of the frequency of the...

Frequency-selectable dual-band wilkinson divider/combiner

A 27GHz Frequency Divider in 0.18μm CMOS Technology

This paper presents a broadband high operating frequency divide-by-2 frequency divider. This divider uses sourcecoupled logic (SCL) with two static loading master-slave D latches which achieves high input operating frequency, high input sensitivity and low power dissipation. This divider can work from 8GHz~ 27GHz and the input power is -40dBm@18GHz. The chip area is 735μm×480μm with only 4.6mW ...

TP 10.5: A 13.4-GHz CMOS Frequency Divider

The above difficulty is alleviated by use ofring-shaped transistors, where the ratio of device width and drain junction capacitance is approximately four times that of a regular layout [4]. However, such a structure proves b neficial if only oneofthedrainorsourceterminalsappearsinthesignalpath. Thus, high-speed divider topologies using stacked devices or pass gates do not necessarily achieve a ...

Frequency locking in the injection-locked frequency divider equation

We consider a model for the injection-locked frequency divider, and study analytically the locking onto rational multiples of the driving frequency. We provide explicit formulae for the width of the plateaux appearing in the devil’s staircase structure of the lockings, and in particular show that the largest plateaux correspond to even integer values for the ratio of the frequency of the drivin...